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Technical Reference Guide
Compaq Armada E500 and Armada V300 Series
First Edition March 2000 Part Number 11QY-0200A-WWEN Compaq Computer Corporation
preface
REFERENCE DOCUMENTS
The following reference documentation and web addresses provide information for the Compaq Armada E500 and Armada V300 computers:
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Compaq Specification #333116, ATI Rage Mobility-P Video Controller #353918, TI PCI1450 Cardbus Controller #342609, ESS 1978SF Maestro-2E Audio Controller #387046, SMSC MSIO, SMSC37N971, Tikki #290725, Flash ROM, 512k x 8, 60ns, 5V #353924, ESS 1920 Audio Codec #258896, Li-Ion Battery Specification Compaq Armada E500 and Armada V300 Maintenance and Service Guide Microsoft Operating System Manual Synaptics Touchpad Interfacing Guide Compaq Web site at http://www. compaq. com Modem commands at http://www. compaq. com/support/portables
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CONTENTS
chapter 1
SYSTEM ARCHITECTURE
Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The primary I2C bus is for battery communication and docking control, and the second I2C bus is for thermal sensor control and EEPROM reading, primarily by the 8051 power management controller.
GPIO9_IN IrCC 2. 0 Block IRTX2 RAW COM TV OUT MUX IR IrDA IRRX TX AUX COM G. P. Data FAST_BIT RX 1 0 "IR_MODE" FRX_SEL FAST GPIO10_OUT 00 01 11 GPIO10 GPIO6_OUT 0 1 GPIO6 1 0 "FRx" 0 1 IRRX IRRX2 0 1 MISC 7 MISC 2 0 1 IRTX GPIO9_OUT 0 1 GPIO9
GPIO8_OUT
GPIO8
IRTX
ASK IR Data Reg Bit 0
FIR
IR Data Reg Bit 1
SONY_MODE
MISC[14:13] MISC[16:15]
Figure 5-6. MSIO Infrared Controller Logic
5-6 Super I/O Controller
Serial UARTs
Two 16550A-compatible UARTS are provided in the MSIO. They can be mapped to any of the standard legacy I/O addresses and interrupts. UART-A is dedicated to the RS-232 transceiver and serial connector on the back of the unit. UART-B interfaces internally to an IrDA-compliant infrared encode/decoder and an IrDA module for serial infrared communications. Information on configuration of the UARTs can be found in the MSIO documentation.
Shared Flash ROM Interface
The MSIO provides a means for the system processor to access the 8051 ROM, so that a single Flash ROM device, shown in Figure 5-7, can be used to store system BIOS as well as 8051 code. To prevent simultaneous access by both processors, the 8051 enters the idle mode and stops its internal clock when the reset-out line (SYS_RESET#_3) is deasserted by the 8051 to PXII4M. The system CPU then has control of the ROM interface and "boots" from the ROM. After executing some very basic test routines, the BIOS code copies itself into system DRAM, begins to execute from DRAM, then starts the 8051 clock again. The system does not need to access the ROM again until it loses power to the DRAM.
Host CPU
ROM nCS
ISA Bus
AD[7:0]
ALE FDC37N97X
LATCH FLASH 512 x 8
ADDR[17:8] nKBWR nKBRD nCE
Figure 5-7. The support functions ensure efficient transfer of audio data streams to and from system memory buffers, providing a system solution with maximum performance and minimal host CPU loading. The architecture enables implementation of communications over the Internet from multiple sources.
Audio Subsystem 6-1
System DRAM
Chipset PCI Bus
CPU
3. 3 V PCI Master SB Pro Legacy Audio
WaveCache APM 1. 2 ACPI 1. 0 PPMI 1. 0 20-Bit AC-Link #1 ES978 Digital I/F EEPROM Interface S/PDIF Output
C24 AC-Link AC'97 CODEC
Mic In Line In Aux 1(CD Audio) Aux 2(DVD) Aux 3(Digital TV) Phone Line Out Headset Out Mono_Out
64-Channel Wave Processor
ES978 Docking Interface EEPROM for Device I/O Customization Digital Audio Output DSP Serial Interface MPEG Audio Analog/Digital Joystick Vol up, Vol down, Mute MIDI Keyboard
Effect Synth
DSP Interface I2S/ZV
HRTF 3-D Positional Audio
Game Port HW Volume MPU-401
Audio Signal Processsor
20-Bit AC-Link #2/ Multiple Serial CODEC Interface SRAM
ROM
Maestro2E
Figure 6-1. ESS Maestro 2E Block Diagram used in the Armada E500 and Armada V300 Computers
The M2E has a variety of audio interfaces. The secondary AC'97 CODEC interface is used to handle the Docking station CODEC interface. The M2E, which operates at 3. 3 volts, has several special features for notebook operation, including compliance with the Advanced Power Management (APM) 1. 2, Advanced Configuration and Power Interface (ACPI) 1. 0, and PCI Power Management Interface (PPMI) 1. 0. The M2E has multiple power-saving modes (D0, D1, D2, and D3) for power-efficiency when the audio system is both active and idle. Its high-quality docking solution supports an AC link-based digital docking solution with its secondary 20-bit AC link. This helps achieve the lowest power consumption in D3 hot mode.
6-2 Audio Subsystem
The device supports full DOS game compatibility for both PC motherboard and add-in card solutions through three hardware implementations: PC/PCI, Distributed DMA (DDMA), and Transparent DMA (TDMA). While PC/ PCI and DDMA are industry-standard protocols for legacy support, ESS's TDMA technology implements DOS game compatibility over the standard PCI 2. 1 bus.
Features
High-Performance PCI Audio Acceleration
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500-MIPS-equivalent dual-engine PCI audio accelerator 64-Channel wavetable synthesis HRTF 3-D positional audio acceleration MultiStream DirectSound and DirectSound3D acceleration Hardware acceleration for DirectMusic, ActiveMovie, and DirectInput API DVD AC-3 speaker virtualization Enhanced effects (reverb, chorus, flange, treble, bass, and 3D stereo expander) Advanced platform for interactive 3-D gaming, DVD movie playback, and Internet communications
Legacy DOS Game Support
Full DOS game compatibility through three hardware implementations: PC/PCI, DDMA, and TDMA s TDMA needs no sideband signals and achieves full DOS game compatibility in the standard PCI 2. 1 bus s Serial IRQ support
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Flexible Audio I/O Interface
20-bit AC'97 1. 03/2. 00 CODEC interface s I2S Zoomed Video interface s Two-button hardware master volume control
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Digital Ready
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Windows 98 WDM acceleration
Power Management
The M2E is a high-performance device with low power consumption. Besides the low power CMOS technology used to process the M2E, various features are designed into the device to provide benefits from popular power-saving techniques. These features and techniques are discussed in this section.
CLKRUN Protocol
The PCI CLKRUN feature is one of the primary methods of power management on the PCI bus interface of the M2E for the notebook computer.
Audio Subsystem 6-3
PCI Power Management Interface (PPMI)
The PCI Power Management Interface (PPMI) specification establishes the infrastructure required to let the operating system control the power of PCI functions. [. . . ] Once the CPU has generated a Quick Start special cycle and moved the Quick Start state, stopping the CPU clock input causes the CPU to enter the Deep Sleep state. To return to Full-On, the CPU clock must be restarted and remain stable for 1 millisecond. From there, the return to full on is completed by de-asserting the STPCLK# signal. Deep Sleep state is used only during Standby because of the 1 millisecond latency.
Processor Thermal Management
The processor temperature is monitored by the CPUTEMP signal. [. . . ]